EDN

At-speed testing made easy

Today's chip designs are getting smaller and bigger. Feature sizes are moving into nanometer geometries, and gate counts are pushing towards the 100M gate mark. Semiconductor companies creating these ...
EDN

Memory fault models and testing

A different set of fault models and testing techniques is required for memory blocks vs. logic. MBIST algorithms that are used to detect faults inside memory are based upon these fault models. This ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...
Semiconductor Engineering

Aging Aware Steepening Metric for the Fault Coverage of a Test Set (Purdue Univ.)

A new technical paper titled “Aging Aware Steepening of the Fault Coverage Curve of a Scan Based Transition Fault Test Set” was published by researchers at Purdue University. “Chip aging may result in ...
Semiconductor Engineering

Challenges And Outlook Of ATE Testing For 2nm SoCs

The transition to the 2nm technology node introduces unprecedented challenges in Automated Test Equipment (ATE) bring-up and manufacturability. As semiconductor devices scale down, the complexity of ...