Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules. Hierarchical DFT divides the design into smaller pieces, creates test ...

As integrated circuit (IC) designs continue to scale, the demand for efficient power management, performance optimization and reliable physical layout modification grows more critical. Meeting these ...

If you can't pick up the schematic and know (at a moderately high level) what the design is supposed to do and how it is supposed to do it, then you have not really done your job as the designer. The ...

Cadence Design Systems has started bringing artificial intelligence (AI) into the fold on its flagship chip design suite to help designers build smaller, faster processors that consume less power and ...