Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D ...

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Yield improvement at sub 100-nm technologies relies on the latest scan test techniques. As IC feature sizes shrink below 90 nm, in-line inspection techniques to determine yield-limiting problems ...

Scan technology was developed as a structured test technique that divided the complex sequential nature of a design into small combinational logic blocks that could be tested individually. This added ...

McFowland III, Edward, Skyler Speakman, and Daniel B. Neill. "Fast Generalized Subset Scan for Anomalous Pattern Detection." Art. 12. Journal of Machine Learning Research 14 (2013): 1533–1561.