EDN

112-Gbps LR SerDes PHY Taps CTLE and Time Interleaved Flash ADC to Reduce ADC Resolution

The right balance of CTLE circuitry and flash ADC sizes and number play a key role in minimizing ADC bits to achieve minimum area and power. The design of a state-of-the-art 112-gigabits-per-second ...
Nature

Time-Interleaved Analog-to-Digital Converters

Time-interleaved analog-to-digital converters (TIADCs) represent a pivotal technology in the advancement of high-speed signal processing. By utilising multiple parallel conversion channels, TIADCs ...
Design-Reuse

UWB Time-interleaved ADC exploiting SAR

The current technology trend for Analog-to- Digital Converters (ADCs) is particularly keen on power reduction, together with high-speed performance. The goal of the paper is to demonstrate that both ...
EDN

Wideband error correction elevates time-interleaved ADCs

Digital mismatch error correction can, in fact, multiply the sampling frequency of state-of-the-art, single-core analog-to-digital converters (ADCs) without the loss ...