EDN

Rethinking statistical timing analysis

A year or two ago, it looked like statistical timing analysis might be the next great new thing in IC design. Now it's less clear–and a debate at the recent International Symposium on Physical Design ...
EDN

Timing analysis tool expands FPGA and board design flows

Chronology has expanded its interactive timing analysis and timing diagram product – TimingDesigner – to include tighter integration with vendor-specific board design and FPGA flows. TimingDesigner ...
Business Insider

Vector Expands Timing Analysis Expertise Through RocqStat Acquisition

NOVI, Mich., Jan. 20, 2026 (GLOBE NEWSWIRE) -- Vector Informatik, a leading solution provider for software-defined systems in automotive and beyond, has acquired the RocqStat software technology and ...
Yahoo Finance

TASKING Delivers Advanced Worst-Case Timing Coupling Analysis and Mitigation for Multicore Designs

The enhanced TASKING integrated toolchain combines compile, debug, and test capabilities to automate the measurement, assessment, and optimization of hidden timing interference in multicore SoCs for ...
New Electronics

Vector strengthens timing analysis portfolio with RocqStat acquisition

Vector Informatik has acquired the RocqStat software technology and specialist team from StatInf, expanding its capabilities in timing analysis and worst‑case execution time (WCET) estimation for ...
Nature

Probabilistic Timing Analysis in Real-Time Systems

Probabilistic timing analysis represents an emergent paradigm in the evaluation of real-time systems, addressing inherent uncertainties that traditional worst-case execution time (WCET) methods ...
Electronic Design

Timing Analysis Rounds The Corner To Statistics

In a perfect world, fabrication of silicon ICs would be a perfectly predictable process. Not only would every chip be absolutely identical, but there would be no variations from wafer to wafer, or lot ...
New Electronics

TASKING unveils enhanced timing analysis tools for multicore embedded systems

TASKING has unveiled new upgrades to its unified development toolchain aimed at improving worst‑case timing and coupling analysis for real‑time multicore embedded systems used in safety‑critical ...
Electronic Design

Timing Checks Go Full Chip

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...