EDN

A tutorial on incremental design using FPGAs from Actel

Regardless of the amount of time and energy FPGA designers invest attempting to create “right-first-time” designs, the functional complexities, performance requirements, and high gate counts of large ...
Business Wire

Mentor Graphics HDL Designer Saves Months of Design Effort with Concurrent HDL Checking

WILSONVILLE, Ore.--(BUSINESS WIRE)--Oct. 7, 2005--Mentor Graphics Corporation (Nasdaq:MENT), the leader in standards-based digital IC design creation, analysis, synthesis, and management tools, today ...
EDN

Mentor provides concurrent HDL checking for FPGA and ASIC designers

Mentor Graphics released a new concurrent design checking and creation environment for FPGA and ASIC design teams working with Verilog, SystemVerilog, and VHDL design languages. The capability is ...